The present invention relates to flash memory devices and more particularly, to a page buffer circuit of a flash memory device and a method for reading and programming data using the page buffer circuit therein.
In general, reading and programming operations in a flash memory device are executed in the unit of page. It is recently proposed a flash memory device including multi-level cells (MLC) that stores pluralities of data bits with the purpose of improving the integration density thereof. As a multi-level cell is able to be programmed with two data bits, it can store one among four data states, i.e., [11], [10], [00], and [01], and is set with one of threshold voltages Vt1˜Vt4 corresponding to the stored data states. Otherwise, a memory cell storing a single data bit is referred to as a single-level cell (SLC).
FIG. 1 is a schematic diagram showing a conventional page buffer circuit of a flash memory device with inputs/outputs to carry out reading and programming operations for the multi-level cell. As shown in FIG. 1, the page buffer circuit 10 includes a bitline selection circuit 11, a precharging circuit 12, a higher-bit register circuit 13, a lower-bit register circuit 14, a data comparing circuit 15, data transmission circuits 16 and 17, a data input circuit 18, and a data output circuit 19. The data input circuit 18 includes NMOS transistors 25 and 26 while the data output circuit 19 includes NMOS transistors 27 and 28. A procedure of reading out a data bit from a multi-level cell (not shown) by the page buffer circuit 10 is as follows in brief.
As an example, it will be explained about the procedure of reading out a lower data bit from the multi-level cell connected to one of bitlines BLe and BLo. The higher and lower bit registers, 13 and 14, are initialized and the precharging circuit 12 charges a sensing node S up to the level of a power source voltage Vcc in advance. Thereafter, the bitline selection circuit 11 connects one of the bitlines BLe and BLo, e.g., BLe, to the sensing node S. And, a read voltage is supplied to a gate of the multi-level cell, which is connected to the bitline BLe, by way of a wordline (not shown). As a result, the bitline BLe and the sensing node S are maintained on the level of the power source voltage Vcc or discharged into the level of a ground voltage in accordance with a data value stored in the multi-level cell that is connected to the bitline BLe. At this time, the lower-bit register 14 detects a voltage at the sensing node S in response to a latch control signal LATCH1 or LATCH2 and stores the detected data bit as a lower data bit therein. The lower data bit stored in the lower-bit register 14 is output to an input/output node Y by the NMOS transistor 28 of the data output circuit 19.
On the other hand, a procedure of reading a higher data bit from a multi-level cell connected to one of the bitlines BLe and BLo is similar to the procedure of reading the lower data bit, but with several points of difference. A first difference between the procedures of reading the higher and lower data bits is that read voltage levels are different from each other. A second difference is that the higher data bit read out from the multi-level cell is output to the data input/output node Y through the NMOS transistor 27 of the data output circuit 19 after being stored in the higher-bit register 13 operating in response to the latch control signal MLATCH1. As such, in the page buffer circuit 10, the lower data bit is stored only in the lower-bit register 14 and the higher data bit is stored only in the higher-bit register 13. This is because the higher-bit register 13 is configured to just detect a voltage of the sensing node S making it impossible to store the inverse value of the detected data bit therein. Thus, the page buffer circuit 10 is inefficient in that point of view. Further, the data output circuit 19 needs to include the NMOS transistor 28 to output the lower data bit to the data input/output node Y, and the NMOS transistor 27 to output the higher data bit to the data input/output node Y.
Next, a procedure of programming a multi-level cell connected to one of the bitlines BLe and BLo by the page buffer circuit 10 is as follows. First, after initializing the higher-bit register 13 and the lower-bit register 14, a data bit to be programmed is stored in the higher-bit register 13. Thereafter, the data bit stored in the higher-bit register 13 is transferred to the higher-bit register 14 by the data transmission circuit 16 and then stored in the lower-bit register 14. One of the bitlines BLe and BLo, e.g., BLe, is connected to the sensing node S by the bitline selection circuit 11. Also, a program voltage is supplied to a gate of the multi-level cell, which is connected to the bitline BLe, by way of a wordline. The data transmission circuit 17 transfers the data bit from the lower-bit register 14 to the sensing node S. As a result, the data bit stored in the lower-bit register 14 is transferred to the bitline BLe connected to the sensing node S and thereby the multi-level cell connected to the bitline BLe is programmed with the transferred data bit. Through the aforementioned procedure, a programming operation for the lower data bit is completed.
In a procedure of programming a higher data bit in the multi-level cell, the higher-bit register 13 and the lower-bit register 14 are first initialized and a data bit to be programmed is stored in the higher-bit register 13. The lower-bit register 14 stores a lower data bit read out from the multi-level cell. Thereafter, the data bit stored in the higher-bit register 13 is transferred to the lower-bit register 14 and then stored therein. The bitline selection circuit 11 connects one of the bitlines BLe and BLo, e.g., BLe, to the sensing node S. Also, a program voltage is supplied to the gate of the multi-level cell, which is connected to the selected bitline BLe, by way of a wordline. The data comparing circuit 15 compares the data bit of the higher-bit register 13 with the data bit of the lower-bit register 14, and then outputs a compared result therefrom to the sensing node S. The resultant data bit by the comparison is stored in the higher-bit register 13. Thereafter, the data comparing circuit 15 compares the data bit of the higher-bit register 13 with the data bit of the lower-bit register 14 again, and then outputs a data bit, which is to be programmed to the sensing node S. As a result, the program data bit is transferred to the bitline BLe that is connected to the sensing node S, so that the multi-level cell connected to the selected bitline BLe is programmed. Through the aforementioned procedure, the programming operation for the multi-level cell connected to the bitline BLe is completed.
As stated above, the page buffer circuit shown in FIG. 1 requires the data comparing circuit 15 to program the higher data bit after programming the lower data bit in the multi-level cell. As a result, as the page buffer circuit 10 includes the NMOS transistors, 27 and 28, of the data output circuit 19, as well as the data comparing circuit 15, it raises the circuit area and increases the size of the flash memory device.